`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:17:54 03/27/2009 
// Design Name: 
// Module Name:    IFID 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module piperegIFID(clk,in,out,in2,out2,reset);
input clk,reset;
input[31:0]in,in2;
output[31:0]out,out2;

reg[31:0] out,out2;

always @(posedge clk)
begin
	if(reset)
		out = 0;
	else
		begin
			out=in;
			out2=in2;
		end
end
endmodule
